LOW POWER VLSI, FULL-CUSTOM DIGITAL IC DESIGN, POWER SUPPLY NOISE

Research Topic -Low Power VLSI, Full-Custom Digital IC Design, Power Supply Noise

The computational capability of Silicon Chips used in our present day computers are badly affected by the noise components generated due to physical scaling of MOS devices over the advancement in semiconductor process technologies. Though the digital circuits in these Silicon Chips have higher noise immunity compared to analog designs, the digital circuits are affected by some ‘man-made’ noise because of their high voltage gain. As matter of fact, ‘man-made’ noise sources hamper the circuit performance more compared to the damage incurred by physical noise sources (which are more prominent in case of analog designs) specially when the digital circuits is configured in sub-nano regime for low supply voltage (≤ 0.8V). Since the computer processor chips majorly comprise of digital circuits, it is really important to alleviate noise for getting their best performance. Among the noise sources in these chips, on-chip power supply noise (PSN) exhibits significant adversity in the performance. Basically, the occurrence of PSN is a large voltage drop (= R×i(t) + L×di/dt) across power supply lines “Vdd” and “Vgnd”, mainly because of Ldi/dt (where ‘L’ is the chip package inductance typically in the range of 5–90pH) while transferring Vdd to on-chip sub-systems. This current ramp (di/dt) is assessed as the culprit for PSN occurrence, but in sub-nano regime it is also the sub-threshold conduction current (IOFF) that has some relevance to the matter. When the processor chip is active for some computational tasks, it burns a current (ION) which is correlated to di/dt. Now this on-to-off current ratio (ION/IOFF) is a big factor in sub-nano regime, as there may be IOFF>ION due to the side-effects of reduced short-channel MOS devices having extremely low threshold voltage (Vth). As a consequence, even when the chip is inactive there is a large current flow depicting significant amount of di/dt keeping the possibility of PSN occurrence. As remedy, researchers have been trying out to address the reduced short-channel effect and control the ION/IOFF ratio through tweaking the MOS device structures. But this approach involves high engineering cost and doesn’t offer generic solution to the problem. In this project, it is aimed to explore some circuit-level or system-level solution for retarding IOFF and hence the PSN occurrence.

The prime factors for PSN occurrence is accounted as flow of instantaneous current “i(t)” and current ramp di/dt that is more often than not instigated by on-chip system clock. Therefore, the aim is to look for better controllability in system clock by developing some strategies for sub-nano CMOS regime. Major focus is development of Ultra-Low-Power (ULP) noise resistant circuital scheme that support the chip to deliver non-erroneous computation.

Department & Campus

Department of Computer Science and Engineering, School of Engineering, Amritapuri

Skillsets Preferred from Applicants

Has to be proficient with full-custom IC Design flow till GDSII export